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KA3012D
4-Channel Motor Driver
Features
* BTL (H-Bridge type linear) 4channel motor driver * Wide dynamic range: - SVCC=12V, PVCC1=5V, RL=8 VOM=4.2V - SVCC=12V, PVCC2=12V, RL=24 VOM=10.4V * Built in level-shift circuit * Built in OP-amp for digital input * Built in thermal shutdown (TSD) circuit * Three independent sources * Low crossover distortion * Built-in reverse rotation prevented * Built-in short breaker
Description
The KA3012D is a monolithic IC, and suitable for 4-CH motor driver which drives sled motor, loading motor, focus & tracking actuator of CD-media system and built in OPamp which can receive digital signal from servo of CDmedia system.
28-SSOPH-375
Typical Applications
* * * * * * Compact disk ROM (CD-ROM) Compact disk RW (CD-RW) Digital video disk ROM (DVD-ROM) Digital video disk RAM (DVD-RAM) Digital video disk player (DVDP) Other compact disk media
Ordering Information
Device KA3012D-02 Package 28-SSOPH-375 Operating Temp. -35 C ~ 85 C -35 C ~ 85 C
KA3012D-02TF 28-SSOPH-375
Rev. 1.0.1 February. 2000.
(c)2000 Fairchild Semiconductor International
1
1 27 2 3 4 5 6 7 26 25 24 23 22
28
CH1-O GND
Pin Assignments
CH1-O
CH4-O
AMP1-O
CH4-O
AMP1-I (-)
AMP4-O
AMP1-I (+)
AMP4-I (-)
BIAS
AMP4-I (+)
SVCC
PVCC1
FIN (GND)
KA3012D
20
MUTE
AMP2-I (+)
AMP2-I (-)
AMP2-O
CH2-O
CH2-O
FIN (GND)
2
21
8 GND 9 10 11 12 13 14
PVCC2
AMP3-I (+)
19 18 17 16 15
AMP3-I (-)
AMP3-O
CH3-O
CH3-O
GND
KA3012D
KA3012D
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name CH1-O CH1-O AMP1-O AMP1-I(-) AMP1-I(+) BIAS SVCC GND MUTE AMP2-I(+) AMP2-I(-) AMP2-O AMP2-O CH2-O GND CH3-O CH3-O AMP3-O AMP3-I(-) AMP3-I(+) PVCC2 PVCC1 AMP4-I(+) AMP4-I(-) AMP4-O CH4-O CH4-O GND I/O O O O I I I I I I O O O O O O I I I I O O O Pin Function Description Drive CH 1 output (-) Drive CH 1 output (+) Op-amp CH 1 output Op-amp CH 1 input (-) OP-amp CH 1 input (+) Bias input Supply voltage (Signal) Ground Mute OP-amp CH 2 input (+) Op-amp CH 2 input (-) Op-amp CH 2 output OP-amp CH 2 output (+) Op-amp CH 2 output (Op-amp CH 2 output) Ground Drive CH 3 output (-) Drive CH 3 output (+) OP-amp CH 3 output Drive CH 3 input (-) Drive CH 3 input (+) Supply voltage (CH 2 & CH 3) Supply voltage (CH1 & CH 4) OP-amp CH 4 input (+) Op-amp CH 4 input (-) Op-amp CH 4 output Drive CH 4 output (+) Drive CH 4 output (-) Ground
3
KA3012D
Internal Block Diagram
AMP4-I (+) AMP3-I (+) AMP4-I (-) AMP3-I (-) AMP4-O AMP3-O PVCC1 PVCC2 CH4-O CH4-O CH3-O CH3-O 16 10k +- 10k -+ +- 13 CH2-O GND GND GND 15 GND PVCC2/2 10k 10k 14 CH2-O
28
27
26
25
24
23
22
21
20
19
18
17
10k
10k 10k
10k
GND
-+
+-
-+ 10k 10k - + + - 10k 10k -+ 10k
PVCC1
PVCC2 +- TSD 10k - + 20k
-+
PVCC1/2
PVCC1/2 - + LEVEL-SHIFT
PVCC2/2
10k
PVCC2 /2 + - LEVEL-SHIFT LEVEL-SHIFT + -
LEVEL-SHIFT - + PVCC1/2 10k -+ +- CH1-O CH1-O 10k 1 2 10k AMP1-I (-) AMP1-O 10k 3 4
+ - +- 10k +- SVCC GND MUTE 20k
PVCC2 /2 10k 10k
5 AMP1-I (+)
6 BIAS
7 SVCC GND
8 GND
9 MUTE
10 AMP2-I (+)
11 AMP2-I (-)
12 AMP2-O
NOTE: The drive channel outputs are determined pre OP-amp output.
4
KA3012D
Equivalent Circuits
Op-amp input Op-amp output
80 AMP-I (+) 5, 10, 20, 23 Pin AMP-I (-) 4, 11, 19, 24 Pin 80 AMP-O 3, 12, 17, 25 Pin
Drive output
Bias
10k 10k
CH-O (2, 13, 17, 26 Pin) Bias (6 Pin) CH-O (1, 14, 16, 27 Pin) 200
1k
Mute
50k Mute (9 Pin) 50k
5
KA3012D
Absolute Maximum Rating (Ta = 25C)
Parameter Supply voltage Power dissipation Operating temperature range Storage temperature range Symbol VCC PD TOPR TSTG Value 15 1.7
note
Unit V W C C
-35 ~ +85 -55 ~ +150
NOTE: 1. When mounted on 50mm x 50mm x 1mm PCB (Phenolic resin material). 2. Power dissipation reduces 13.6mW / C for using above Ta=25C. 3. Do not exceed PD and SOA (Safe operating area).
Power Dissipation Curve
Pd (mW) 3,000 2,000
1,000
SOA
0 0 25 50 75 85 100 125 150 175 Ambient temperature, Ta [C]
Recommended Operating Condition (Ta = 25C)
Parameter Supply voltage Symbol SVCC, VCC1, VCC2 Min. 4.5 Typ. Max. 13.2 Unit V
6
KA3012D
Electrical Characteristics
(Ta=25C, VCC1=VCC2=5V, RL=8) Parameter DRIVE CIRCUIT Quiescent current 1 Quiescent current 2 Output offset voltage 1 Output offset voltage 2 Max.output amplitude 1 Max.output amplitude 2 Voltage gain 1 ICC1 ICC2 VOO1 VOO2 VOM1 VOM2 GVC1 No load, Mute off No load, Mute on CH 1, CH 4 CH 2, CH 3 CH 1, CH 4 CH 2, CH 3 (RL=24) VIN=0.1VRMS, 1kHz, sinewave. Input OP-amp Buffer CH 1, CH 4 VIN=0.1VRMS, 1kHz, sinewave. Input OP-amp Buffer CH 2, CH 3 Input op-amp output VCC & 1.2k Input op-amp output GND & 1.2k 100kHz square-wave 2Vp-p output -70 -90 3 8 10 15 0 4.2 10.4 12.0 20 500 70 90 14 mA uA mA mV V V dB Symbol Conditions Min. Typ. Max. Units
Voltage gain 2
GVC2
16
18
20
dB
Mute on voltage Mute off voltage INPUT OP-AMP CIRCUIT Input offset voltage Input bias current High level output voltage Low level output voltage Output driving current sink Output driving current source Slew rate
VMon VMoff VOFOP IBOP VOHOP VOLOP ISINK ISOURCE SR
2.0 -10 10 1 1 -
0 10.9 1.1 1
0.5 10 300 1.8 -
V V mV nA V V mA mA V / s
7
KA3012D
Application Information
1. MUTE
Pin #9 High Low Open
Mute circuit Turn-on Turn-off Turn-off
9 Output driver bias
* When the voltage level of the mute pin is above 2V, the mute circuit is activated so that the output circuit will be muted. * When the mute pin #9 is open or the voltage of the mute pin #9 is below 0.5V, the mute circuit is deactivated and the output circuit operates normally. * When the mute circuit is activated, the voltage level of output pins becomes 1/2VCC (approximately). 2. TSD (THERMAL SHUTDOWN)
VREF BG Output driver bias
R11
Q11 R12
* If the chip temperature rises above 175C, then the TSD (Thermal shutdown) circuit is activated and the output circuit is muted. * The VREF BG is the output voltage of the band-gap-referenced bias in circuit and acts as the input voltage of the TSD circuit. * The base-emitter voltage of the TR,Q11 is designed to turn-on at 460mA. VBE = VREF BG x R12 / (R11 + R12)=460mV * When the chip temperature rises up to 175C, the turn-on voltage of the Q11 drops down to 460mV. (Hysteresis: 25C) and Q11 turns on so the output circuit is muted.
8
KA3012D
3. DRIVER
+I BIAS (6 Pin) Pre-amp AMP-I (+) (5, 10, 20, 23 Pin) - AMP-I (-) (4, 11, 19, 24 Pin) AMP-O (3, 12, 18, 25 Pin) + 10k + - AMP Level shift
+ -
Buffer -V M +V
Q1
Q2
10k -I + - Buffer
CH-O (1, 14, Q3 16, 27 Pin)
CH-O (2, 13, 17, 26 Pin)
Q4
* The gain of pre-op. Amplifier can be changed by manipulating amp input resistor or feedback resistor. * The voltage, VREF, is the reference voltage given by the bias voltage of the pin #6. * The level shift produces the current due to the difference between the pre amp output signal and the arbitrary reference (bias) signal. (The current produced as +I and -I is fed into the driver buffer. (CH1/CH4) The current produced as +2I and -2I is fed into the driver buffer. (CH2/CH3) * Driver buffer drives the power TR of the output stage according to the state of the input signal. * The output stage is the BTL driver and the motor is rotating in forward direction by operating TR Q1 and TR Q4.On the other hand, if TR Q2 and TR Q3 is operating, the motor is rotating in reverse direction. * When the output voltage of Pre-Amp (Pin 3, 12, 18, 25) is below the VREF, then the direction of the motor is in forward. * When the output voltage of Pre-Amp (Pin 3, 12, 18, 25) is above the VREF, then the direction of the motor in reverse. * The gain (AV) of the drive circuit is as follows.
4V IN A V = 20 log ------------ = 12 ( dB ) (CH1/CH4) V IN 4V IN A V = 20 log ------------ = 18 ( dB ) (CH1/CH4) V IN
4. CONNECT A BY-PASS CAPACITOR, 0.1F BETWEEN THE SUPPLY VOLTAGE SOURCE.
VCC1 7 104
5. RADIATION FIN IS CONNECTING TO THE INTERNAL GND OF THE PACKAGE. CONNECT THE FIN TO THE EXTERNAL GND.
9
KA3012D
Typical Performance Characteristics
VCC vs ICC (No load)
14 12 10 ICC (mA) 8 6 4 2 0 0 2 4 6 8 VCC (V) 10 12 14 16
AMP-I (+) vs OUTPUT VOLTAGE
Figures can be obtained by changing of AMP-I (+) from 0V to 5V, shows the voltage difference between CH-O and CH-O. (AMP-I (+) and AMP-O are shorted.)
1. CH 1 and CH 4 (12dB)
5 4 3 Output Voltage Vom1(V) 2 1 0 -1 -2 -3 -4 -5 0 1 2
AMP-I (+)(V)
2. CH 2 and CH 3 (18dB)
12 10 8 Output Voltage Vom1(V) 3 4 5 6 4 2 0 -2 -4 -6 -8 -10 -12 0 1 2 3 4 5
AMP-I (+)(V)
VCC vs Gain
1. CH 1 and CH 4 (12dB)
15
2. CH 2 and CH 3 (18dB)
21
14 13
Gain1(dB) Gain1(dB)
20
19
12 11
18
17
10 9 4 5 6 7 8 9
V CC ( V )
16
15
0
11
12
13
14
4
5
6
7
8
9
V CC ( V )
0
11
12
13
14
10
KA3012D
Test Circuits
RL4 V
10F
PVCC1
10F
PVCC2
RL3 RL3' V
OPIN (+)
OPIN (-)
OPOUT
OPIN (+)
OPIN (-)
OPOUT
SW3
SW4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
KA3012D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OPOUT
OPIN (+)
OPIN (-)
OPIN (+)
OPIN (-)
OPOUT
SW1
SW2 RL2 RL2 '
A V RL1 Bias 2.5V 10F SVCC 12V VMUTE
V
OPIN (+)
OPIN (-)
OPOUT VCC
SW5 1 V 1M VIN3 VIN1 VIN2 3 2
V 1 SW6 10F 3 VIN5 VIN4 2
V 1.2k 1M 3 V 1 SW7 2
11
KA3012D
Typical Application Circuits
SERVO PREAMP
MICOM
FOCUS
TRACKING
BIAS
SLED
LOADING (SPINDLE)
MUTE
10k 10k M 10k GND 10k 21 20 19 18 17 16 15
28
27
26
25
24
23
22
KA3012D
1
2
3
4
5
6
7 GND
8
9
10
11
12
13
14
10k
10k M
10k
10k
BIAS
12
KA3012D
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 12/1/00 0.0m 001 Stock#DSxxxxxxxx 2000 Fairchild Semiconductor International
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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